1. Field of the Invention
The present invention relates to a semiconductor device using a MOS transistor.
2. Description of the Related Art
A dynamic RAM (DRY) is known as a semiconductor device. It is expected that a recently developed DRAM having a vertical MOS transistor and having a small surface area will increase integration density.
FIG. 1A shows an external appearance of the vertical memory cell applied to the DRAM, and FIG. 1B is a cross-sectional view taken along line 1B--1B in FIG. 1A. The vertical memory cell comprises one MOS capacitor and one MOS transistor. A columnar semiconductor layer 93 is formed continuously from a semiconductor substrate 91. The MOS capacitor is formed at a bottom portion of the semiconductor layer 93. Specifically, an n.sup.+ layer 98, which will function as a substrate-side electrode, and a plate electrode 94 are formed around the bottom portion of the semiconductor layer 93, with a capacitor insulating film (not shown) interposed between the n.sup.+ layer 98 and the plate electrode 94. Numeral 92 denotes an inversion preventing layer. On the other hand, the MOS transistor is formed at a top portion of the semiconductor layer 93. Specifically, a gate electrode 95 is formed around the top portion of the semiconductor layer 93, with a gate insulating film (not shown) being interposed. An n.sup.+ layer 96, which will function as a source or drain of the MOS transistor, is formed on the surface of the semiconductor layer 93, and a bit line 97 is connected to the n.sup.+ layer 96.
FIG. 2A is a plan view showing a part of an equalizer circuit of a DRAM using a vertical transistor, and FIG. 2B is a cross-sectional view taken along line 2B--2B in FIG. 2A. This vertical transistor corresponds to the MOS transistor formed at the top portion of the semiconductor layer 93 in FIGS. 1A and 1B, and common parts are denoted by like reference numerals. Symbols BL and /BL denote bit lines. Symbol EL denotes an equalizer wire through which an equalizer signal is supplied. The bit line /BL is connected to a diffusion layer 98, which will function as a source or drain of the semiconductor substrate 91, via a contact layer 99. Since the contact layer 99 is formed on the diffusion layer 98 so that the bit line/BL may become on a level with the bit line BL, the bit lines BL and /BL can be formed easily.
The above MOS transistor, however, has the following problem. When the contact layer 99 is formed on the source/drain diffusion layer 98, an alignment error may occur between the contact layer 99 and the source/drain diffusion layer 98. At this time, if a contact area between the contact layer 99 and diffusion layer 98 decreases, a desired contact resistance will not be obtained. Even if a small alignment error occurs, at least a predetermined contact area needs to be maintained, and for this purpose it is conventionally required to form the contact layer 99 with a diameter of 1.5 F or more (F=minimum processing dimension). Besides, in order to prevent undesirable connection between the contact layer 99 and equalizer wire EL, it is conventionally required to form the contact layer 99 at a distance F or more from the semiconductor layer 93.
Because of various limitations mentioned above, even if the vertical transistor is adopted in the DRAM equalizer circuit, remarkable reduction in area is not expected. Of course, this problem occurs in peripheral circuits, other than the equalizer circuit, which require transistors. Moreover, even the vertical transistor cannot be used in a sense amplifier which should desirably be formed between the bit lines BL and/BL which are arrange at an interval F for increasing integration density.
Furthermore, the DRAM adopting the vertical memory cell has the following problem. FIG. 3 is a cross-sectional view showing two adjacent vertical memory cells within a cell array. Since the vertical memory cell has a structure in which the gate electrode 95 is formed around the columnar semiconductor layer 93, the gate electrodes 95 of the adjacent vertical memory cells are opposed to each other. Consequently, a parasitic capacitance is produced between the gate electrodes 95 of the adjacent vertical memory cells, and a leak current flows. In addition, the word line 95 has a shunt structure for reducing resistance. Specifically, the gate wires are put in contact with shunt wires A at predetermined intervals. A coupling ratio C.sub.WL--WL between the word lines 95 is expressed by equation (1), when the capacitance of the entire word wires is CWL, the capacitance between the gate wires is C.sub.1, and the capacitance between the shunt wires is C.sub.2 : EQU C.sub.WL--WL =(C.sub.1 +C.sub.2)/C.sub.WL ( 1)
The capacitance C.sub.WL of the entire word lines is substantially equal to the capacitance C.sub.2 between the shunt wires, whether the memory cell structure is an SGT structure or a conventional structure. However, the capacitance C.sub.1 between the gate wires varies greatly, depending on the memory cell structure. In the case of the conventional memory cell, the MOS transistor has a flat structure and therefore the capacitance C.sub.1 between the gate wires is low.
Besides, the parasitic capacitance C.sub.1 between the gate wires is not negligible, since the gate electrodes of the adjacent vertical memory cells are opposed to each other. Thus, the potential level of the nonselected word line located adjacent to the selected word line increases. As described above, the reliability of the DRAM using the vertical memory cell is lower than the DRAM using the conventional flat memory cell.